Altera / Intel MAX? V CPLD

Altera MAX? V CPLD 是業(yè)界功耗最小、成本最低的 CPLD，具有多種強大的新功能，與競爭CPLD相比，總功耗降低了50%。Altera MAX V 采用了獨特的非易失體系結構，是業(yè)界密度最大的CPLD。此外，MAX V 集成了閃存、RAM、振蕩器和鎖相環(huán)等多種以前的外部功能，在很多情況下，與競爭CPLD相比，MAX V 在單位引腳布局中提供更多的I/O和邏輯，而價(jià)格相當。MAX V 還使用了綠色封裝技術(shù)，封裝大小只有20mm2。Quartus II? Software v.10.1 支持 MAX V CPLD。該軟件可使您提升效能，進(jìn)行更快地仿真，更迅速地開(kāi)發(fā)電路板，盡快達到時(shí)序逼近。

In addition, the MAX V integrates many functions that were previously external, such as flash, RAM, oscillators, and phase-locked loops. In many cases, it delivers more I/Os and logic per footprint at the same price as competitive CPLDs.

The Altera MAX V utilizes green packaging technology, with packages as small as 20 mm2. MAX V CPLDs are supported by Quartus II? Software v.10.1, which allows productivity enhancements resulting in faster simulation, faster board bring-up, and faster timing closure.

特性

· Extended battery life with static power as low as 45uW

· As few as one power supply (Vcc-core) required, which also lowers bill of materials (BOM) costs

· Digital PLLs (DPLLs), which enable flexible implementation of designs requiring frequency multiplication or phase shifting

· In-system programming (ISP) lets you program the device while it is in operation, so you can perform in-field updates without affecting overall system operation

· User flash memory, embedded flash memory that provides non-volatile memory storage of critical system information

應用

· Wireline and Wireless

o I/O expansion

· Industrial and Military

o Interface bridging (i.e., between different voltage and I/O standards)

· Consumer

o Power management control, sequencing, or monitoring

· Broadcast

o Initialization control (i.e., of DSPs, processors)

BLOCK DIAGRAM

ADDITIONAL RESOURCES

· Max V Handbook

· Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs

產(chǎn)品型號